publication
Publication details
- System Performance Comparison of Stencil Operations with the Convey HC-1 (Julian Kunkel, Petra Nerge), Technical Reports (1), Research Group: Scientific Computing, University of Hamburg (Deutsches Klimarechenzentrum GmbH, Bundesstraße 45a, D-20146 Hamburg), 2010-11-16
Publication details – URL
Abstract
In this technical report our first experiences with a Convey HC-1 are documented. Several stencil application kernels are evaluated and related work in the area of CPUs, GPUs and FPGAs is discussed. Performance of the C and Fortran stencil benchmarks in single and double precision are reported. Benchmarks were run on Blizzard – the IBM supercomputer at DKRZ –, the working group's Intel Westmere cluster and the Convey HC-1 provided at KIT.
With the Vector personality, performance of the Convey system is not convincing. However, there lies potential in programming custom personalities. The major issue is to approximate performance of an implementation on a FPGA before the time consuming implementation is performed.
BibTeX
@techreport{SPCOSOWTCH10, author = {Julian Kunkel and Petra Nerge}, title = {{System Performance Comparison of Stencil Operations with the Convey HC-1}}, year = {2010}, month = {11}, publisher = {Research Group: Scientific Computing, University of Hamburg}, address = {Deutsches Klimarechenzentrum GmbH, Bundesstraße 45a, D-20146 Hamburg}, series = {Technical Reports}, number = {1}, abstract = {In this technical report our first experiences with a Convey HC-1 are documented. Several stencil application kernels are evaluated and related work in the area of CPUs, GPUs and FPGAs is discussed. Performance of the C and Fortran stencil benchmarks in single and double precision are reported. Benchmarks were run on Blizzard -- the IBM supercomputer at DKRZ --, the working group's Intel Westmere cluster and the Convey HC-1 provided at KIT. With the Vector personality, performance of the Convey system is not convincing. However, there lies potential in programming custom personalities. The major issue is to approximate performance of an implementation on a FPGA before the time consuming implementation is performed.}, url = {http://www.wr.informatik.uni-hamburg.de/_media/research/publications/2010/spcosowtch10-system_performance_comparison_of_stencil_operations_with_the_convey_hc_1.pdf}, }
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